AS&D Inc. in support of NASA/GSFC – USA
Thursday, Aug. 30 – 13:40h – Malbec B
SBCCI INVITED TALK:
FPGA Mitigation Strategies for Critical Space Applications
Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being implemented. They range from weaker EDAC circuits that save area and power to strong mitigation strategies that come at a great expense to the system.
Regarding FPGA and ASIC EDAC insertion, there is no “one-solution-fits-all.” The user must be aware of a variety of concerns. As an example, each FPGA device-type requires a different mitigation strategy for various reasons.
This presentation will focus on the susceptibilities of a variety of FPGA types and ASICs in the avionics and space environment. In addition, the user will be provided information on what are the optimal mitigation strategies per FPGA and ASIC. Internal device component mitigation versus system level mitigation will also be discussed.
Melanie Berg received her MS degree in Electrical Engineering from the University of Pittsburgh in 1990. Since 1988, she has been a designer, verification engineer, instructor, and reviewer, for a variety of high-speed multi-million gate ASIC and FPGA development teams. One of her more visible accomplishments was her role as a designer and verification engineer in the NASA sponsored New Horizons Pluto and Beyond Mission.
Ms. Berg is currently a member of the Radiation Effects and Analysis group at NASA Goddard Space Flight Center (GSFC). Her NASA/GSFC responsibilities include: developing flight designs, performing design reviews, investigating FPGA/ASIC mitigation strategies for critical missions, and calculating mission survivability/reliability predictions.
Ms. Berg has published and presented several papers concerning such topics as: Reliable Synchronous Design Methodology, Robust Verification Techniques, Mitigation Strategies for Critical Circuitry, Survivability Predictions, Hardness Assurance for Space Flight Systems, and ASIC/FPGA Trust/Security Schemes.