Programação
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Horário
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Dia | ||||
| Segunda – 06/05 | Terça – 07/05 | Quarta – 08/05 | Quinta – 09/05 | Sexta – 10/05 | |
| 8:00 – 8:30 | sem atividade | Projeto Digital Introdutório – Rafael Soares | SIM 2 – Reliability ( 6 papers) | SIM 5 – Visual Signal Processing I ( 6 papers) | SIM 9 – Visual Signal Processing II (7 papers) |
| 8:30 – 9:00 | sem atividade | Projeto Digital Introdutório – Rafael Soares | SIM 2 – Reliability ( 6 papers) | SIM 5 – Visual Signal Processing I ( 6 papers) | SIM 9 – Visual Signal Processing II (7 papers) |
| 09:00 – 9:30 | sem atividade | Projeto Digital Introdutório – Rafael Soares | SIM 2 – Reliability ( 6 papers) | SIM 5 – Visual Signal Processing I ( 6 papers) | SIM 9 – Visual Signal Processing II (7 papers) |
| 9:30 – 10:00 | sem atividade | Coffee-Break | Coffee-Break | Coffee-Break | Coffee-Break |
| 10:00 – 10:30 | sem atividade | CAD Introdutório – Maicon Cardoso | SIM 3 – Energy-efficient Design (7 papers) | SIM 6 – Neural Networks and Machine Learning (6 papers) | SIM 10 – Analog and mixed-signal (7 papers) |
| 10:30 – 11:00 | sem atividade | CAD Introdutório – Maicon Cardoso | SIM 3 – Energy-efficient Design (7 papers) | SIM 6 – Neural Networks and Machine Learning (6 papers) | SIM 10 – Analog and mixed-signal (7 papers) |
| 11:00 – 11:30 | sem atividade | CAD Introdutório – Maicon Cardoso | SIM 3 – Energy-efficient Design (7 papers) | SIM 6 – Neural Networks and Machine Learning (6 papers) | SIM 10 – Analog and mixed-signal (7 papers) |
| 11:30 – 12:00 | sem atividade | Sponsor (Chipus) – 10 minutos | Livre para sponsors – 15 minutos | Sponsor (Silvaco) – 20 minutos | Livre para sponsors – 15 minutos |
| 12:00 – 12:30 | sem atividade | Almoço | Almoço | Almoço | Almoço |
| 12:30-13:00 | sem atividade | Almoço | Almoço | Almoço | Almoço |
| 13:00 -13:30 | Abertura | Almoço | Almoço | Almoço | Almoço |
| 13:30 -14:00 | Evolução do Transistor (Sergio Bampi) | Introdução a circuitos análogicos – Hamilton Klimach | SIM 4 – Best Paper Candidates I (4 papers) | SIM 7 – Radiofrequency (7 papers) | Painel PPGs |
| 14:00 – 14:30 | Evolução do Transistor (Sergio Bampi) | Introdução a circuitos análogicos – Hamilton Klimach | SIM 4 – Best Paper Candidates I (4 papers) | SIM 7 – Radiofrequency (7 papers) | Painel PPGs |
| 14:30 – 15:00 | Evolução do Transistor (Sergio Bampi) | Introdução a circuitos análogicos – Hamilton Klimach | Rede Neurais FPGA – Fernanda Kastensmidt | SIM 7 – Radiofrequency (7 papers) | Painel PPGs |
| 15:00 – 15:30 | Coffee – Break | Coffee-Break | Rede Neurais FPGA – Fernanda Kastensmidt | Coffee-Break | Encerramento |
| 15:30 – 16:00 | Sponsor (EnSilica) – 10 minutos | Introdução a Circuitos de RF – Sandro Binsfeld Ferreira | Coffee-Break | SIM 8 – Best paper Candidates II (4 papers) | Encerramento |
| 16:00 – 16:30 | Introdução às Portas Lógicas (Cláudio Diniz) | Introdução a Circuitos de RF – Sandro Binsfeld Ferreira | Video Coding – Luciano Agostini | SIM 8 – Best paper Candidates II (4 papers) | |
| 16:30 – 17:00 | Introdução às Portas Lógicas (Cláudio Diniz) | Introdução a Circuitos de RF – Sandro Binsfeld Ferreira | Video Coding – Luciano Agostini | Tirando do Papel – Alcides Costa | |
| 17:00 – 17:30 | Introdução às Portas Lógicas (Cláudio Diniz) | SIM 1 – EDA and Other Tools (5 papers) | 75 anos de CASS, 40 anos de SIM e 25 anos de EMICRO | Tirando do Papel – Alcides Costa | |
| 17:30 – 18:00 | Livre para sponsors – 30 minutos | SIM 1 – EDA and Other Tools (5 papers) | IEEE CASS Student Meet-up e social event | Livre para sponsors – 30 minutos | |
| 18:00 – 18:30 | SIM 1 – EDA and Other Tools (5 papers) | IEEE CASS Student Meet-up e social event | Livre para sponsors – 30 minutos | ||
| 18:30 – 19:00 | IEEE CASS Student Meet-up e social event | Jantar do evento EMICRO/SIM 2024 | |||
| 19:00 – 22:00 | Jantar do evento EMICRO/SIM 2024 | ||||
Programação Artigos SIM 2024
| SIM1 17:00 – 18:15 |
EDA and Other Tools ( 5 papers) | ||
| Horário | ID | Título | Autores |
| 17:00 | 4 | Efficiency and Computational Cost Analysis of the Geometry-based Point Cloud Encoder | Gustavo H Rehbein (UFPel)*; Eduardo de Figueiredo Costa (UFPel); Leandro Tavares (UFPel); Cristiano Santos (UFPel); Guilherme Correa (UFPel); Marcelo S Porto (UFPel) |
| 17:15 | 8 | Evaluation of LBP Learning for U-Net Based Road Semantic Segmentation | Mauricio K Yui (UEL)*;Leonimer Flávio de Melo (UEL)* |
| 17:30 | 44 | Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet Forwarding | Nathan A Guimarães (UFRGS)*; Pablo Rodrigues (UFRGS); Weverton Cordeiro (UFRGS); Jose Rodrigo Azambuja (UFRGS) |
| 17:45 | 54 | A Parallel JPEG Pleno Baseline Block-Based Profile Light Field Encoder using OpenMP | Ismael Seidel (UFSC)*; André Filipe da Silva Fernandes (UFSC); José Luis Guntzel (UFSC) |
| 18:00 | 55 | Abstracting Logic Synthesis Features with Node Centrality for Routing Congestion Prediction | Augusto Berndt (UFSC)*; Cristina Meinhardt (UFSC) |
| SIM2 8:00 – 9:30 |
Reliability (6 papers) |
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| Horário | ID | Título | Autores |
| 08:00 | 13 | Exploring Security Threats by Hardware-Faults in Approximate Arithmetic Computing | Eloisa Barros (UFPel ); Morgana Macedo Azevedo da Rosa (UFPel )*; Eduardo Antonio da Costa (UCPel); Rafael Soares (UFPel); Sergio Bampi (UFRGS) |
| 08:15 | 15 | Robustness Analysis of Different 2:1 Multiplexer Designs Against Single Event Transient Faults | Ana Flávia D Reis (FURG)*; Rafael Schvittz (FURG) |
| 08:30 | 23 | Determining Neutron-based static cross-section of a SRAM-based FPGA in a simplified setup | Julia Willow Benvenutti (UFRGS)*; Fernanda Kastensmidt (UFRGS); Lívia Streit (UFRGS); Fábio Benevenuti (UFRGS) |
| 08:45 | 24 | Analyzing the Reliability of a Low-cost RISC-V Synthesized into a SRAM-based FPGA under Fault Injection | Eduardo Domingo Marañon Aguilar (UFRGS)*; Eduardo Domingo Marañon Aguilar (UFRGS); Nixon Ortiz (UFRGS); Fabio Benevenuti (UFRGS); Fernanda Lima (UFRGS) |
| 09:00 | 26 | Predicting Soft Error Susceptibility in Integrated Circuits: A Methodology for Cross-Section Estimation | Clayton Rodrigues Farias (UFRGS)*; Paulo Butzen (UFRGS); Tiago Balen (UFRGS) |
| 09:15 | 48 | Implementation of Design for Testability Techniques in a Low-Power RISC-V Processor | Eduardo A Barcelos (UnB)*; Gilmar Beserra (UnB); Jones Silva (UnB); Hercules Santos (UnB) |
| SIM2 10:00 – 11:45 |
Energy-efficient Design (7 papers) | ||
| Horário | ID | Título | Autores |
| 10:00 | 2 | An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression | Rodrigo Lopes (Universidade Federal de Pelotas ) Arthur Cardozo (Universidade Federal de Pelotas ) Morgana Macedo Azevedo da Rosa (Universidade Federal de Pelotas )* Rafael Soares (Universidade Federal de Pelotas) Eduardo Antonio da Costa (Universidade Católica de Pelotas) Sergio Bampi (UFRGS) |
| 10:15 | 7 | Exploring Ultra Compact 4:2 Compressors on Power-efficient Multipliers | Vinicius Zanandrea (UFSC)*; Cristina Meinhardt (UFSC) |
| 10:30 | 10 | Approximate Storage Evaluation at Inter-Frame Prediction in VVC Encoding Process | Yasmin S Camargo (UFPel)*; Felipe Sampaio (IFRS); Daniel Palomino (UFPel); Bruno Zatt (UFPel); Renira Soares (UFPel); Matheus M. Isquierdo (UFPel) |
| 10:45 | 25 | Bit-Depth Optimized Transposition Buffer Design for the AV1 2D-DCT Transform | Jelson Stoelben Rodrigues (UFPel)*; Jones W. Goebel (UFPel); Luciano Volcan Agostini (UFPel – UFPel); Bruno Zatt (UFPel); Marcelo S Porto (UFPel) |
| 11:00 | 42 | An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing | Nicolas de Oliveira (UFPel); Morgana Macedo Azevedo da Rosa (UFPel )*; Henrique Seidel (UFPel); Eduardo Antonio da Costa (UCPel); Sergio Almeida ( UCPel); Rafael Soares (Nil) |
| 11:15 | 56 | Reconfigurable Approximate Multiplier by Multiple Leading One-Bit Blocks | João M Bedin (UFRGS)*; Pedro T. L. Pereira (UFRGS), Rodrigo N. Wuerdig (UFRGS), and Sergio Bampi (UFRGS) |
| 11:30 | 61 | Hardware Acceleration for Approximate Version of SATD with Rectangular Hadamard Matrix Sizes | Juliana Rodrigues de Vargas (UFRGS)*; Claudio M Diniz (UFRGS) |
| SIM4 13:30 – 14:30 |
Best Paper Candidates I (4 papers) |
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| Horário | ID | Título | Autores |
| 13:30 | 1 | New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies | Leonardo Antonietti (UFPel ); Rodrigo Lopes (UFPel ); Morgana Macedo Azevedo da Rosa (UFPel )*; Eduardo Antonio da Costa (UCPel); Rafael Soares (Nil); Sergio Bampi (Nil) |
| 13:45 | 14 | An Energy-Efficient StEFCal VLSI Design with Approximate Squarer and Divider Units | Morgana Macedo Azevedo da Rosa (UFPel )*; Eduardo Antonio da Costa (UCPel); Rafael Soares (UFPel); Sergio Bampi (UFRGS) |
| 14:00 | 20 | Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design | GABRIEL BITENCOURT CARDOSO (Unipampa)*; Daniel Tomm (Unipampa); Jiovana Gomes (UFRGS); Rodrigo Wuerdig (UFRGS); Sergio Bampi (UFRGS); Fábio Ramos (Unipampa) |
| 14:15 | 45 | Performance Analysis of Multiple Transform Selection in the VVC Encoder | Caroline S Camargo (UFPel)*; Bianca Silveira (UFPel); Guilherme Correa (UFPel) |
| SIM5 08:00 – 09:30 |
Visual Signal Processing I ( 6 papers) |
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| Horário | ID | Título | Autores |
| 08:00 | 21 | Coding Efficiency and Time Evaluation of Apple A15 Bionic Chipset HEVC Encoder | Vítor Costa (UFPel)*; Murilo Perleberg (UFPel); Luciano Volcan Agostini (UFPel); Marcelo S Porto (UFPel) |
| 08:15 | 22 | 4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor | Marcello M Muñoz (UFPel)*; Murilo Perleberg (UFPel); Luciano Volcan Agostini (UFPel ); Guilherme Correa (UFPel); Marcelo S Porto (UFPel) |
| 08:30 | 27 | An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow | Murilo Perleberg (UFPel)*; Marcello M Muñoz (UFPel); Denis Maass (UFPel); Vladimir Afonso (IFSul); Luciano Volcan Agostini (UFPel); Marcelo S Porto (UFPel) |
| 08:45 | 34 | Evaluation of AV1 encoder tools for pixel interpolation in fractional inter-frame prediction | Daiane Fonseca Freitas (UFPel)*; Patrick Rosa (UFPel); Leonardo Müller ( UFPel); Cláudio Diniz (UFRGS); Mateus Grellert (UFRGS); Guilherme Correa (UFPel) |
| 09:00 | 35 | A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees | Ramiro G S Viana (UFPel)*; Marta B Loose (UFPel ); Rafael Ferreira (UFPel); Marcelo S Porto (UFPel); Guilherme Correa (UFPel); Luciano Volcan Agostini (UFPel) |
| 09:15 | 46 | High-Throughput Hardware Design for Linear Equation System Solving of VVC Affine Prediction | Denis Maass (UFPel)*; Marcello M Muñoz (UFPel); Murilo Perleberg (UFPel); Luciano Volcan Agostini (UFPel – UFPel); Marcelo S Porto (UFPel) |
| SIM6 10:00 – 11:30 |
Neural Networks and Machine Learning (6 papers) |
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| Horário | ID | Título | Autores |
| 10:00 | 3 | Test Zone Search Optimization in VVC Inter-Frame Prediction Using Machine Learning | Ramiro G S Viana (UFPel)*; Fernando Sagrilo (IFFar); Rafael Ferreira (UFPel); Marta B Loose (UFPel ); Marcelo S Porto (UFPel); Guilherme Correa (UFPel); Luciano Volcan Agostini (UFPel) |
| 10:15 | 6 | Fast ISP Mode Decision Solution for the VVC Intra Prediction based on Machine Learning | Larissa Araújo (UFPel)*; Adson Duarte (UFPel); Bruno Zatt (UFPel); Guilherme Correa (UFPel); Daniel Palomino (UFPel) |
| 10:30 | 11 | Video Quality Enhancement Based on Multi-Domain Spatio-Temporal Deformable Fusion Model | Garibaldi da Silveira Júnior (UFPel)*; Gilberto Kreisler (UFPel); Bruno Zatt (UFPel); Daniel Palomino (UFPel); Guilherme Correa (UFPel) |
| 10:45 | 31 | MAC Convolutional 2D Generic filter | Talita A Borges (UFRGS)*; Paulo Butzen (UFRGS); Claudio M Diniz (UFRGS); Leonardo B Soares (IFRS) |
| 11:00 | 50 | Quality-Complexity Analysis of Autoencoders for Neural-Network Image Compression | Vitor A Arguilar (UFRGS)*; Leonardo Augusto (UFRGS); Mateus Grellert (UFRGS) |
| 11:15 | 51 | Design and Synthesis of Accelerators for Neural Networks with an I2C Interface: a Preliminary Study | TIAGO VIER PRETO (UFRGS)*; Mateus Grellert (UFRGS) |
| SIM7 13:30 – 15:15 |
Radiofrequency (7 papers) |
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| Horário | ID | Título | Autores |
| 13:30 | 17 | Energy Harvesting applied to Smart Farms | João Pedro G Dytz (FURG)*; Vagner Rosa (FURG); Vinicius Pedro (FURG); Paulo Butzen (UFRGS) |
| 13:45 | 28 |
Memory Polynomials with Sparse Delays and Nonlinearities Applied to Power Amplifier Mathematical Modeling
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Maria Eduarda Rizo (UFPR)*; Eduardo Lima (UFPR) |
| 14:00 | 30 | Comparison of 4-transistor and 5-transistor stacked RF CMOS power amplifier | MOISES ALVES GUERGOLET (UFPR)*; Favero Santos (SENAI); Bernardo Leite (UFPR) |
| 14:15 | 37 | Adaptively-biased RF CMOS Power Amplifier | Luciano A Oliveira (UFPR)*; Bernardo Leite (UFPR) |
| 14:30 | 39 | Characterization of a VLC Circuit Based on Photovoltaic Cells for Indoor Positioning System | Vitória Alves Monteiro (UNIPAMPA)*; Tawan Chrysther dos Santos (UNIPAMPA); Cristian Muller (UNIPAMPA); Paulo Aguirre (UNIPAMPA); Alessandro Girardi (UNIPAMPA) |
| 14:45 | 57 | Analysis of a Cold Start Circuit for Indoor Energy Harvesting in 65-nm CMOS | Diego Maran de Mattos (UNIPAMPA)*; Paulo Aguirre (UNIPAMPA); Lucas Severo (ITA); Alessandro Girardi (UNIPAMPA) |
| 15:00 | 58 | A 13.56 MHz CMOS Active Rectifier With Dynamically Controllable Comparator for WPT-Powered IMDs | Claudio Ernani da Costa Pedroso Júnior (UNIPAMPA)*; Alessandro Girardi (UNIPAMPA); Paulo Aguirre (UNIPAMPA) |
| SIM8 15:30-16:30 |
Best paper Candidates II (4 papers) |
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| Horário | ID | Título | Autores |
| 15:30 | 12 | A Machine Learning-Based Solution to Accelerate the Intra Mode Decision for the VVC Standard | Adson Duarte (UFPel)*; Bruno Zatt (UFPel); Guilherme Correa (UFPel); Daniel Palomino (UFPel) |
| 15:45 | 16 | Placement Refinement Strategies for Security Closure | Marcelo F Danigno (FURG)*; Mateus Fogaca (Cadence Design Systems); Rafael Schvittz (FURG); Paulo Butzen (UFRGS) |
| 16:00 | 32 | Memory Access Analysis of the Reconstructed Frames in VVenC Motion Estimation | Matheus M Isquierdo (UFPel)*; Felipe Sampaio (IFRS); Bruno Zatt (UFPel); Daniel Palomino (UFPel) |
| 16:15 | 49 | Machine Learning-Based Decision Solution for G-PCC | Eduardo de Figueiredo Costa (UFPel)*; Leandro Tavares (UFPel); Guilherme Correa (UFPel); Cristiano Santos (UFPel); Marcelo S Porto (UFPel) |
| SIM9 08:00 – 09:45 |
Visual Signal Processing II (7 papers) |
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| Horário | ID | Título | Autores |
| 08:00 | 5 | Improving the AV1 Global Warped Motion Compensation Execution Time | WILLIAM KOLODZIEJSKI (UFPEL)*; Robson Domanski (UFPel); Luciano Volcan Agostini (UFPel – UFPel) |
| 08:15 | 9 | Computational Effort Reduction of VVC Inter-Frame Prediction: A Literature Review | Marta B Loose (UFPel )*; Ramiro G S Viana (UFPel – UFPel); Bianca Nunes Coelho (UFPEL); Guilherme Correa (UFPel); Luciano Volcan Agostini (UFPel – UFPel) |
| 08:30 | 18 | Mapping and monitoring Normalized Difference Vegetation Index (NDVI) in pasture areas | Victório Mariani (UFRGS )*; Altamiro Susin (UFRGS); Tiago Weber (UFRGS) |
| 08:45 | 19 | Survey of Complexity-Aware Artificial Intelligence-based Solutions for Versatile Video Coding | Ruhan Avila da Conceição (UFPel)*; Marcelo S Porto (UFPel); Luciano Volcan Agostini (UFPel) |
| 09:00 | 36 | Data Acquisition and Processing Systems for Spectrophotometric Applications: A Review | Michael dos Santos Rodrigues (UFRGS)*; Altamiro Amadeu Susin (UFRGS); Prof◦. Dr◦. Alexsandro Cristovão Bonatto (IFRS) |
| 09:15 | 40 | Performance Analysis of Hardware-Accelerated HEVC Encoders | Sara Henssler (IFSul); Marcio Spenst (IFSul); Luciano Volcan Agostini (UFPel – UFPel); Marcel Correa (IFSul)* |
| 09:30 | 41 | Applying Video Frame Interpolation to Light Field Coding: an Early Study | André Beims Bräscher (UFSC)*; Gabriela Furtado da Silveira (UFSC); Luiz Henrique Cancellier (UFSC); Ismael Seidel (UFSC); José Luis Guntzel (UFSC) |
| SIM10 10:00 – 11:45 |
Analog and mixed-signal (7 papers) |
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| Horário | ID | Título | Autores |
| 10:00 | 29 | Electrical and Physical Design of a 15-pF Load Analog Output Buffer for Intra-Die Signal Sensing | Beatriz Estefania Hatschbach Rezende (UNIPAMPA)*; Crístian Müller (UNIPAMPA); Lucas Compassi Severo (ITA); Alessandro Gonçalves Girardi (UNIPAMPA); Paulo Aguirre (UNIPAMPA) |
| 10:15 | 33 | A 103.7-µW 4-bit Rail-to-Rail Flash ADC in 65-nm CMOS | Tawan Chrysther dos Santos (UNIPAMPA)*; Alessandro Girardi (UNIPAMPA); Paulo Aguirre (UNIPAMPA) |
| 10:30 | 38 | A Low-Power and Low-Noise Open-Loop 7 MHz Relaxation Oscillator | João Frischenbruder Sulzbach (UFRGS)*; Hamilton D Klimach (UFRGS) |
| 10:45 | 43 | Applying Oscillation Based Test Method for Evaluating and Sorting Commercial Integrated Circuits | Luis Duarte (UFRGS)*; Tiago Balen (UFRGS); Marcelo Lubaszewski (UFRGS) |
| 11:00 | 52 | A 5-V 125-kHz Third-Order Continuous-Time Sigma-Delta Modulator in 130-nm BCD Technology |
Renan Dotto Oliveira (UNIPAMPA)*; Tawan Chrysther dos Santos (UNIPAMPA); Matheus B S Carvalho (UNIPAMPA); Cristian Muller (UNIPAMPA); Lucas Compassi Severo (ITA); Alessandro Girardi (UNIPAMPA); Paulo Aguirre (UNIPAMPA)
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| 11:15 | 59 | A Simple 10-bit Incremental Sigma-Delta Modulator for Multi Channel Analog to Digital Conversion | Martim Presser (UFSM)*; Felipe de Souza e Silva (UFSM); Cesar Augusto Prior (UFSM); Henrique Friggi Beque (UFSM) |
| 11:30 | 47 | Evaluation of the CIC Filter Order in Decimation Filters for Sigma-Delta ADCs | Otavio Elias Viana de Freitas (UNIPAMPA)*; Critian Muller (UNIPAMPA) |