Publicações
Produção bibliográfica organizada por ano e, dentro de cada ano, por tipo de publicação. Os títulos são apresentados em sua forma oficial, e o nome de Luciano Volcan Agostini aparece em destaque nas listas de autores.
112Artigos em periódicos
404Trabalhos em eventos
8Livros
6Capítulos
4Patentes
98Prêmios e títulos
Fonte: Currículo Lattes atualizado em 29/07/2026.
Publicações por ano
Os anos estão apresentados em ordem decrescente. Dentro de cada ano, as publicações são separadas em artigos em periódicos, trabalhos em eventos, livros, capítulos de livros e patentes, quando houver registros.
2026 (10 publicações)
Artigos em periódicos (4)
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Quantitative assessment of inter-frame prediction in versatile video coding standard
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On the Impact of Quantization Precision and Calibration Settings Applied to the SSF Neural Video Decoder
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Accelerating Versatile Video Coding via Decision-Tree-Based Fast Affine Motion Estimation
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A Coding-Efficiency Analysis of HEVC Encoder Embedded in High-End Mobile Chipsets
Trabalhos em eventos (6)
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Hardware-Friendly Machine-Learning-Based Fast AV1 Overlapped Block Motion Compensation
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FastMIP-360: A Lightweight Decision Tree for Pruning VVC MIP in 360° Videos
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Energy-Efficient Neural Video Coding via a High-Throughput Hardware Design for Pointwise Convolution and LUT-based WSiLU
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Assessing the Domain Gap: Evaluation of STDF for Enhancing Videos Compressed by Neural Codecs
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A Rate-Distortion-Complexity Analysis of Neural Video CODECs
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A FHD@30fps Hardware Design for WSiLU Activation Function for Neural Video Coding
2025 (26 publicações)
Artigos em periódicos (6)
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Hardware Architecture Design for Power-Efficient Motion Estimation over Compressed Block Data
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FastGW: A Machine Learning-Based Early Skip for the AV1 Global Warped Motion Compensation
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DM-FIFS: A Dual-Model Machine-Learning Method for Fast Interpolation Filter Search in AV1 Encoding
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An Efficient Hardware Design for the VVC Prediction Refinement with Optical Flow
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A Real-Time Hardware for LES Solving and deltaMV Calculation in VVC Affine Prediction
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A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor
Trabalhos em eventos (19)
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Traditional vs. Neural Video Codecs: Compression Efficiency, Visual Artifacts, and Quality Analysis Beyond PSNR
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Real-Time UHD 4K Hardware Design for the Gradient-Based Search of the VVC Affine ME
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Platform-Independent Hardware Design for Low-Power Neural Video Hyperprior Decoding
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Hardware Design for VVC Angular Intra Prediction Modes with Coding Efficiency Awareness
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Fast VVC Test Zone Search and Affine Motion Estimation Using Machine Learning
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Fast VVC Angular Intra-Prediction for 360° Videos Based on Decision Trees
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Fast VVC Affine Motion Estimation Using a Hardware-Friendly Machine Learning Method
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Fast Heuristic for VVC Intra-frame Prediction Targeting 360° Video Formats
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Fast AV1 LocalWarped Motion Compensation Using Machine Learning
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FIFS: A Machine Learning-Based Fast AV1 Interpolation Filter Search
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Evaluation of Tile-based Parallelism in VVC Encoders for 360-degree Videos
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Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors
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Efficient Hardware Design for Compressed Blocks SAD Calculation in VVC Motion Estimation
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Cross-Platform Neural Video Coding: A Case Study
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Análise da Eficiência de Compressão do Codificador HEVC Embarcado no Smartphone Samsung Galaxy S23 Plus
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A Power-Efficient Architecture for LES Solving and ¿MV Calculation of VVC Affine Prediction
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A Lightweight I3D-Based Approach for Real-Time Brazilian Sign Language Recognition
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A Hardware Architecture for Smoothing Filters in H.266/VVC Intra-Prediction
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A Fast and Hardware-Friendly CTB-Based Approach for VVC Affine Motion Estimation
Livros publicados ou organizados (1)
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Hardware Design for 3D Video Coding – Energy-efficient and High-throughput Architectures for Multiview Plus Depth Video Content
2024 (10 publicações)
Artigos em periódicos (2)
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Memory-Centered Motion Estimation System With CTB-Based Full-Splitting Algorithm
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Adaptive complexity control for AV1 video encoder using machine learning
Trabalhos em eventos (8)
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Speeding Up the AV1 Global Warped Motion Compensation
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High-Throughput Hardware Design for the Complete VVC Angular Intra Prediction
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Coding Efficiency and Time Evaluation of Apple A15 Bionic Chipset HEVC Encoder
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Bit-Width Optimized Transposition Buffer Design for the AV1 2D-DCT Transform
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A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System Solving
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A Hardware-Friendly Fast VVC Test Zone Search Algorithm Using Machine Learning
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A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees
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A Coding-Efficiency-Aware Fast Heuristic for VVC Intra-Frame Prediction Targeting 360° Videos
2023 (15 publicações)
Artigos em periódicos (6)
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Learning-based bypass zone search algorithm for fast motion estimation
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High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters
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Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction
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Efficient Dedicated Hardware Design System for the VVC Low-Frequency Non-Separable Transform
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Complexity and compression efficiency analysis of libaom AV1 video codec
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A High-Throughput Hardware Design for the AV1 Decoder Intraprediction
Trabalhos em eventos (9)
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Learning-Based Fast VVC Affine Motion Estimation
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High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation
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High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation
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High-Throughput Design for a Multi-Size DCT-II Targeting the AV1 Encoder
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Hardware Design for the Affine Motion Compensation of the VVC Standard
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Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding
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Efficient Architecture for VVC Angular Intra Prediction based on a Hardware-Friendly Heuristic
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An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow
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4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor
2022 (19 publicações)
Artigos em periódicos (5)
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Ultra-High Definition AV1 FME Interpolation Architectures Exploring Approximate Computing
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Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction
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Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction
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FastInter360: A Fast Inter Mode Decision for HEVC 360 Video Coding
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Configurable Fast Block Partitioning for VVC Intra Coding Using Light Gradient Boosting Machine
Trabalhos em eventos (13)
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VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis
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Multi-Objective optimized Complexity Control for the AV1 Video Encoder
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Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction
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Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder
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Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder
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GM-RF: An Av1 Intra-Frame Fast Decision Based On Random Forest
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Fast Transform Decision Scheme for VVC Intra-Frame Prediction Using Decision Trees
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Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination
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Direction-Based Fast Mode Decision and Hardware Design for the AV1 Intra Prediction
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An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder
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A Learning-Based Framework for Depth Perception using Dense Light Fields
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A High-Throughput Design for the H.266/VVC Low-Frequency Non-Separable Transform
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A Hardware-Friendly and Configurable Heuristic Targeting VVC Inter-Frame Prediction
Livros publicados ou organizados (1)
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Versatile Video Coding (VVC) – Machine Learning and Heuristics
2021 (17 publicações)
Artigos em periódicos (8)
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Using curved angular intra-frame prediction to improve video coding efficiency
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Performance analysis of VVC intra coding
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Modern Video Coding: Methods, Challenges and Systems
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Low-energy motion estimation memory system with dynamic management
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Hardware and coding efficiency assessment of 3D-HEVC DIS tool using alternative similarity criteria
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Fast block partitioning scheme for chrominance intra prediction of versatile video coding standard
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Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing
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AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design
Trabalhos em eventos (9)
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Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation
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Learning-Based Complexity Reduction Scheme for VVC Intra-Frame Prediction
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Infusion Profiler: an Architecture for Generation of Operational Profiles for Intravenous Infusions
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Inferência dos Perfis de Infusão em Sistemas Intravenosos: Uma Abordagem Empregando Técnicas de Aprendizagem de Máquina
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Fast Block Size Decision for HEVC Encoders with On-the-Fly Trained Classifiers
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Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
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ESA360 – Early SKIP Mode Decision Algorithm for Fast ERP 360 Video Coding
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Configurable Power/Quality-Aware Hardware Design for the AV1 Directional Intra Frame Prediction
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Analysis of VVC Intra Prediction Block Partitioning Structure
2020 (37 publicações)
Artigos em periódicos (15)
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UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders
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Tile Adaptation for Workload Balancing of 3D-HEVC Encoder in Homogeneous Multicore Systems
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Speedup evaluation of HEVC parallel video coding using Tiles
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Real-Time and Low-Power HEVC Deblocking Filter Architecture Targeting 8K UHD @ 60fps Videos
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Parallelism exploration for 3D high-efficiency video coding depth modeling mode one
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Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction
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Memory-aware Workload Balancing Technique based on Decision Trees for Parallel HEVC Video Coding
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High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction
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High-Throughput Hardware Design for 3D-HEVC Disparity Estimation
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Fast 3D-HEVC Depth Map Encoding Using Machine Learning
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Direct and Semi-Direct Frame Partitioning Mapping for Computation and Energy-Aware HEVC Transrating
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Complexity and compression efficiency assessment of 3D-HEVC encoder
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A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes
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6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design
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3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos
Trabalhos em eventos (19)
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Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Video Coding
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Memory Profiling of H.266 Versatile Video Coding Standard
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Memory Assessment Of Versatile Video Coding
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Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC
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High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos
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Fast Partitioning Decision Scheme for Versatile Video Coding Intra-Frame Prediction
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Fast Intra Mode Decision for 3D-HEVC Depth Map Coding using Decision Trees
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Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos
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ERP-Based CTU Splitting Early Termination for Intra Prediction of 360 videos
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Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding
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Complexity Analysis Of VVC Intra Coding
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Avaliação do Uso de Aprendizagem de Máquina na Inferência de Perfis de Infusões Intravenosas
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An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder
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An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs
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ASIC Solution for the Directional Intra Prediction of the AV1 Encoder Targeting UHD 4K Videos
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A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool
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A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change
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4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding
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2PSA: An Optimized and Flexible Power-Precision Scalable Adder
Livros publicados ou organizados (1)
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Algorithms for Efficient and Fast 3D-HEVC Depth Map Encoding
Patentes (2)
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Método Rápido para Estimação de Movimento em Vídeo Digital Utilizando Árvores de Decisão
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Método Rápido para Estimação de Movimento em Vídeo Digital Utilizando Árvores de Decisão
2019 (31 publicações)
Artigos em periódicos (8)
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The Impacts of Equirectangular 360-degrees Videos in the Intra-Frame Prediction of HEVC
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Quality and Energy-Aware HEVC Transrating Based on Machine Learning
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Performance Analysis of Depth Intra-Coding in 3D-HEVC
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High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation
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Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse
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Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy
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Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design
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Analysis of parallel encoding using tiles in 3D High Efficiency Video Coding
Trabalhos em eventos (22)
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Time Reduction on 3D-HEVC Depth Maps Coding using Static Decision Trees Built Through Data Mining
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TITAN: Tile Timing-Aware Balancing Algorithm for Speeding Up the 3D-HEVC Intra Coding
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SPODi: Simulador do Perfil Operacional de Dispositivos Intravenosos para Auxilio à Tomada de Decisões Médicas
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Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders
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Online Machine Learning for Fast Coding Unit Decisions in HEVC
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Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture
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Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors
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IPBN: alerts management in intravenous electromedical devices using bayesian networks
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High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes
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Hardware design of DC/CFL intra-prediction decoder for the AV1 codec
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HEVC Video Coding Using Decision Trees for a Memory-Friendly Tiles Workload Balance
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FastIntra360: A Fast Intra-Prediction Technique for 360-Degrees Video Coding
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Fast partitioning decision making for prediction units on H.264-to-HEVC transcoding using machine learning
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Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation
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Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs
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Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders
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Complexity Scalable HEVC-to-AV1 Transcoding Based on Coding Tree Depth Inheritance
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Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators
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A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design
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A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors
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A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor
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A Fast Local Mode Decision for the HEVC Intra Prediction Based on Direction Detection
Capítulos de livros (1)
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Real-time architectures for 3D video coding
2018 (31 publicações)
Artigos em periódicos (7)
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Speedup-Oriented History-Based Tiling Algorithm for the HEVC Standard Targeting an Efficient Parallelism Exploration
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Reference frame context-adaptive variable-length coder: a real-time hardware-friendly approach for lossless external memory bandwidth reduction in current video-coding systems
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High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator
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Exploration of depth modeling mode one lossless wedgelets storage strategies for 3D-high efficiency video coding
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Energy and Rate-Aware Design for HEVC Motion Estimation Based on Pareto Efficiency
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Block-level fast coding scheme for depth maps in three-dimensional high efficiency video coding
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A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction
Trabalhos em eventos (23)
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Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator
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Octagonal-Axis Raster Pattern for Improved Test Zone Search Motion Estimation
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Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC
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Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4
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Low-Power HEVC 1-D IDCT Hardware Architecture
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Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos
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Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video Standards
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LF-CAE: Context-Adaptive Encoding for Lenslet Light Fields Using HEVC
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Intravenous Electromedical Equipment: A Proposal to Improve Accuracy in Generating Alerts
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High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design
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High Throughput Multiplierless Architecture for VP9 Fractional Motion Estimation
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High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos
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Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVC
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Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC
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Fast and energy-efficient HEVC transrating based on frame partitioning inheritance
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Fast 3D-Hevc Depth Maps Intra-Frame Prediction Using Data Mining
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Energy-Aware HEVC Transrating based on Frame Partitioning Inheritance
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DCDM-Intra: Dynamically Configurable 3D-HEVC Depth Maps Intra-Frame Prediction Algorithm
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Configurable Cache Memory Architecture for Low-Energy Motion Estimation
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Coding- and Energy-Efficient FME Hardware Design
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ASIC power-estimation accuracy evaluation: A case study using video-coding architectures
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A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation
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3D-HEVC DMM-1 Parallelism Exploration Targeting Multicore Systems
Patentes (1)
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Método de Otimização em Codificação de Imagens Tridimensionais e Codificador para Imagens Tridimensionais
2017 (19 publicações)
Artigos em periódicos (3)
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Real-time scalable hardware architecture for 3D-HEVC bipartition modes
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Fast an Low-Power Hardware Design for HEVC Fractional Motion Estimation
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Energy-aware scheme for the 3D-HEVC depth maps prediction
Trabalhos em eventos (15)
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Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection
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Multiple early-termination scheme for TZ search algorithm based on data mining and decision trees
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Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip
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Low-Area Scalable Hardware Architecture for DMM-1 Encoder of 3D-HEVC Video Coding Standard
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High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos
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High Speedup Tiling Algorithm for Parallel HEVC Encoding
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Energy-efficient motion estimation with approximate arithmetic
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Energy evaluation of the HEVC decoding for different encoding configurations
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Edge-aware depth motion estimation ¿ A complexity reduction scheme for 3D-HEVC
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Depth modeling modes complexity control system for the 3D-HEVC video encoder
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Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification
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Complexity reduction by modes reduction in RD-list for intra-frame prediction in 3D-HEVC depth maps
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Characterizing energy consumption in software HEVC encoders: HM vs x265
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Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation
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A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding
Patentes (1)
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Conjunto de Algoritmos de Baixa Complexidade para Particionamento de Coding Units na Codificação de Vídeos Digitais Segundo o Padrão H.265/HEVC
2016 (26 publicações)
Artigos em periódicos (6)
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Pareto-Based Method for High Efficiency Video Coding With Limited Encoding Time
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Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy
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Fast intra prediction algorithm based on texture analysis for 3D-HEVC encoders
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Fast coding tree structure decision for HEVC based on classification trees
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DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard
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Complexity scalability for real-time HEVC encoders
Trabalhos em eventos (18)
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Squarer exploration for energy-efficient sum of squared differences
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Speedup-aware history-based tiling algorithm for the HEVC standard
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Solutions for DMM-1 complexity reduction in 3D-HEVC based on gradient calculation
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Real-time simplified edge detector architecture for 3D-HEVC depth maps coding
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Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding
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Rate-constrained successive elimination of Hadamard-based SATDs
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Pareto-based energy control for the HEVC encoder
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High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards
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Fast H.264/AVC to HEVC transcoder based on data mining and decision trees
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Energy-efficient SATD for beyond HEVC
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Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC
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Energy analisys of motion estimation memory transference on embedded processors
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Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme
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Coarse grain partial distortion elimination for Hadamard ME in HEVC
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An efficient sub-sample interpolator hardware for VP9-10 standards
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An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs
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A parallel Motion Estimation solution for heterogeneous System on Chip
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3D-HEVC depth maps intra prediction complexity analysis
Livros publicados ou organizados (1)
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Complexity-Aware High Efficiency Video Coding
Capítulos de livros (1)
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Arquitetura de Hardware para um Compressor de Quadros de Referência em Codificadores de Vídeos Digitais
2015 (18 publicações)
Artigos em periódicos (4)
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Hardware-friendly HEVC motion estimation: new algorithms and efficient VLSI designs targeting high definition videos
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Fast HEVC Encoding Decisions Using Data Mining
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Exploring Optimized Hadamard Methods to Design Energy-Efficient SATD Architectures
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DMMFast: a complexity reduction scheme for three-dimensional high-efficiency video coding intraframe depth map coding
Trabalhos em eventos (13)
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S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC
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Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos
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Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation
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Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications
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Fast mode selection algorithm based on texture analysis for 3D-HEVC intra prediction
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Encoding time control system for HEVC based on Rate-Distortion-Complexity analysis
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Compressor de Quadros de Referência de Alta Eficiência para Codificadores de Vídeo de Alta Definição
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Complexity reduction for the 3D-HEVC depth maps coding
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A real-time architecture for reference frame compression for high definition video coders
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A multi-standard interpolation hardware solution for H.264 and HEVC
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A multi-standard interpolation filter for motion compensated prediction on high definition videos
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A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder
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A Hardware Architecture for an HEVC Motion Compensation Luminance Interpolator
Capítulos de livros (1)
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Arquiteturas de Hardware Dedicadas para as Transformadas Discretas dos Cossenos do Padrão HEVC
2014 (25 publicações)
Artigos em periódicos (3)
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Low-Cost and High-Throughput Hardware Design for the HEVC 16×16 2-D DCT Transform
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Inter-view prediction of intra mode decision forhigh-efficiency video coding-based multiviewvideo coding
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HEVC intra prediction acceleration based on texture direction and prediction unit modes reuse
Trabalhos em eventos (21)
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Sample adaptive offset filter hardware design for HEVC encoder
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Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders
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Overview and quality analysis in 3D-HEVC emergent video coding standard
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Memory energy consumption reduction in video coding systems
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Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding
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Hardware Design for HEVC-based Adaptive Loop Filter
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HEVC Fractional Motion Estimation complexity reduction for real-time applications
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Four-step algorithm for early termination in HEVC inter-frame prediction based on decision trees
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Cost Function Optimization and its Hardware Design for the Sample Adaptive Offset of HEVC Standard
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Configurable hardware design for the HEVC-based Adaptive Loop Filter
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Complexity reduction of depth intra coding for 3D video extension of HEVC
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Complexity reduction for 3D-HEVC depth maps intra-frame prediction using simplified edge detector algorithm
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Classification-based early termination for coding tree structure decision in HEVC
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Arquitetura VLSI de Baixa Potência para um Compressor de Quadros de Referência
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An efficient reference frame compression approach for video coding systems
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A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders
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A low-complexity and lossless reference frame encoder algorithm for video coding
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A complexity reduction algorithm for depth maps intra prediction on the 3D-HEVC
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A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4
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A Method for Early-Splitting of HEVC Inter Blocks Based on Decision Trees
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A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems
Capítulos de livros (1)
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Computational Resource Management for Video Coding in Mobile Environments
2013 (28 publicações)
Artigos em periódicos (3)
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Iterative random search: a new local minima resistant algorithm for motion estimation in high-definition videos
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Implementation and Performance Evaluation of a Media Decoder with Hardware Acceleration Support Targeting High Definition Streams in the SBTVD Ginga Middleware
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A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4:2:2 profile
Trabalhos em eventos (25)
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Speeding Up HEVC Intra Coding Based on Tree Depth Inter-levels Correlation Structure
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Simplified HEVC FME Interpolation Unit Targeting a Low Cost and High Throughput Hardware Design
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Low cost and high throughput FME interpolation for the HEVC emerging video coding standard
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Inter-view prediction of coding tree depth for HEVC-based multiview video coding
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High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit
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Hardware design for the 32×32 IDCT of the HEVC video coding standard
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HEVC intra mode decision acceleration based on tree depth levels relationship
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HEVC Intra Coding Acceleration Based on Tree Inter-level Mode Correlation
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Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block
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Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding
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Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding
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ES&IS: Enhanced Spread and Iterative Search hardware-friendly motion estimation algorithm for the HEVC Standard
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Desenvolvimento em Hardware de Arquiteturas Otimizadas para as Transformadas Discretas dos Cossenos Segundo o Padrão HEVC de Codificação de Vídeo
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Desenvolvimento de Arquitetura para Estimação de Movimento Fracionária do Padrão HEVC
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Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding
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Constrained encoding structures for computational complexity scalability in HEVC
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Computational complexity control for HEVC based on coding tree spatio-temporal correlation
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Complexity control of HEVC through quadtree depth estimation
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Coding Tree Depth Estimation for Complexity Reduction of HEVC
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An energy-efficient hardware design for lossless reference frame compression in video coders
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An adaptive workload management scheme for HEVC encoding
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A real time high definition architecture for the Variable-Length Reference Frame Decoder
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A lossless approach for external memory bandwidth reduction in video coding systems and its VLSI architecture
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A hardware friedly motion estimation algorithm for the emergent HEVC standard and its low power hardware design
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A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications
2012 (36 publicações)
Artigos em periódicos (13)
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Uma Arquitetura Rápida de Somador Binário de Alta Eficiência Energética
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Sample-Level Filtering Order for High-Throughput and Memory-Aware H.264 Deblocking Filter
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Power efficient SDS motion estimation architecture using dynamic iteration control and hierarchical adder compressors for real time HDTV video coding
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Performance and Computational Complexity Assessment of High-Efficiency Video Encoders
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Optimizing transistor networks using a graph-based technique
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New Motion Estimation Algorithms and its VLSI architectures for Real Time High Definition Video Coding
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MSBSD: Um Algoritmo para Decisão Rápida na Inter-Predição em Codificadores HEVC
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Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder
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Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos
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Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware
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DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation
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Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders
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A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos
Trabalhos em eventos (22)
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Very High Throughput FPGA Design for Vertical Rotational Transform of HEVC Emergent Video Coding Standard
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Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design
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Real Time QHDTV Motion Estimation Architecture Design for DMPDS Algorithm
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Projeto em Hardware com Baixo Custo e Elevada Taxa de Processamento para a Transformada DCT 16×16 do Padrão Emergente de Codificação de Vídeos HEVC
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Projeto de Hardware Com Elevada Taxa de Processamento Para Estimação de Movimento Fracionária Segundo o Padrão HEVC
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New Quarter Random Search Motion Estimation Algorithm: A Great Quality-Cost Trade-Off
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NSP Kernel Finder – Uma Metodologia para Geração de Redes de Transistores Não-Série-Paralelas para a Tecnologia CMOS
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Motion compensated tree depth limitation for complexity control of HEVC encoding
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Motion Vectors Merging: Low Complexity Prediction Unit Decision Heuristic for the Inter‐Prediction of HEVC Encoders
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Memory Efficient FPGA Implementation of Motion and Disparity Estimation for the Multiview Video Coding
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Memory Bandwidth Reduction in Video Coding Systems Through Context Adaptive Lossless Reference Frame Compression
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Low Cost and High Throughput Multiplierless Design of a 16 Point 1-D DCT of the New HEVC Video Coding Standard
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High performance hardware architectures for the inverse Rotational Transform of the emerging HEVC standard
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High Throughput Hardware Design for the Adaptive Loop Filter of the Emerging HEVC Video Coding
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Fast HEVC Intra Prediction Mode Decision Based on Edge Direction Information
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Fast HEVC Intra Mode Decision Based on Dominant Edge Evaluation and Tree Structure Dependencies
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FPGA Based Design for Motion Vector Predicton in H.264/AVC Encoders Targeting HD1080p Resolution
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Dynamic Tree-Depth Adjustment for Low Power HEVC Encoders
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Adaptive Coding Tree for Complexity Control of High Efficiency Video Encoders
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A memory aware and multiplierless VLSI architecture for the complete Intra Prediction of the HEVC emerging standard
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A high performance and low memory bandwidth architecture for motion estimation targeting high definition digital videos
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A High Quality Hardware Friendly Motion Estimation Algorithm Focusing in HD Videos
Livros publicados ou organizados (1)
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SPL 2012 – VIII Southern Programmable Logic Conference
2011 (31 publicações)
Artigos em periódicos (6)
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Two fast multi-point search algorithms for high quality motion estimation in high resolution videos
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Galaxy Random Search: Algoritmo e Arquitetura para Estimação de Movimento em Vídeos de Alta Definição
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Complexity control of high efficiency video encoders for power-constrained devices
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A comparative analysis of media processing component implementations for the Brazilian digital TV middleware
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A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension
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A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Trabalhos em eventos (25)
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Two Novel Algorithms for High Quality Motion Estimation in High Definition Video Sequences
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Test and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios
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SHBS: A Heuristic for Fast Inter Mode Decision of H.264/AVC Standard Targeting VLSI Design
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Run-Time Adaptive Energy-Aware Motion and Disparity Estimation in Multiview Video Coding
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Otimizações em Redes de Transistores Usando uma Estratégia de Compartilhamento de Arestas em uma Estrutura de Grafo
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Otimizações em Redes de Transistores Usando um Método de Compartilhamento de Arestas em uma Estrutura de Grafo
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Multilevel Data Reuse Scheme for Off-Chip Memory Accesses Reduction Applied to a Motion Estimation Architecture
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Implementation and Performance Evaluation of a Media Decoder with Hardware Acceleration Support Targeting High Definition Streams in the SBTVD Ginga Middleware
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High efficient motion estimation architecture with integrated Motion Compensation and FME support
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High Throughput 4×4 and 8×8 SATD Similarity Criteria Architectures for Video Coding Application
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Hardware Design for the New Galaxy Random Search Motion Estimation Algorithm Focusing in HD Videos
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H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos
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Arquitetura para Estimação de Movimento do Padrão H.264/AVC com Algoritmo Diamond Search e Precisão de Quarterpixel
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Arquitetura para Estimação de Movimento do Padrão H.264/AVC com Algoritmo Diamond Search e Precisão de Quarter-Pixel
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An Efficient Memory Hierarchy for Full Search Motion Estimation on High Definition Digital Videos
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An Efficient ME Architecture for High Definition Videos Using the New MPDS Algorithm
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Algorithm and Hardware Design of a Fast Intra-Frame Mode Decision Module for H.264/AVC Encoders
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A1CSA: An Energy-Efficient Fast Adder Architecture for Cell-Based VLSI Design
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A real time and power efficient HDTV motion estimation architecture using adder-compressors
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A real time HDTV motion estimation architecture for the new MPDS algorithm
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A graph-based technique to optimize transistor networks
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A Multilevel Data Reuse Scheme for Motion Estimation and Its VLSI Design
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A High Throughput H.264/AVC Intra-Frame Encoding Loop Architecture for HD1080p
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A H.264/AVC Quarter-Pixel Motion Estimation Refinement Architecture Targeting High Resolution Video
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A Fast Random Based Motion Estimation Search Algorithm
2010 (22 publicações)
Artigos em periódicos (1)
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High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard
Trabalhos em eventos (20)
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Variable Block Size Motion Estimation Architecture with Integrated Motion Compensation with Fast Bottom-Up Mode Decision for the H.264/AVC Video Coding Standard
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Timing and interface communication analysis of H.264/AVC encoder using SystemC model
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SOPTMIZER: Uma Ferramenta para Desenvolvimento de Redes de Transistores Usando uma Abordagem Baseada em Grafo
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Motion Vector Predictor Architecture for H.264/AVC Main Profile Targeting HDTV 1080p
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Memory-Aware Multiple Reference Frame Motion Estimation for the H.264/AVC Standard
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Interlayer Intra Prediction Architecture for Scalable Extension of H.264/AVC Standard
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Homogeneity and Distortion-Based Intra Mode Decision Architecture for H.264/AVC
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Hardware Design for Fast Intermode Decision and for Residues Generaton in a Variable Block Size Motion Estimation Compliant with the H.264/AVC Video Coding Standard
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Evaluating Two Implementations of the Component Responsible for Decoding Video and Audio in the Brazilian Digital TV Middleware
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Efficiency Evaluation and Architecture Design of SSD Unities for the H.264/AVC Standard
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Desenvolvimento e Validação de um Player de Vídeo para a TV Digital
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Desenvolvimento de uma Arquitetura para Interpolação de Half-Pixels segundo o padrão H.264/AVC
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Avaliação de Eficiência e Desenvolvimento de Arquiteturas para o Cálculo do SSD Segundo o Padrão H.264/AVC
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Arquitetura em Hardware para a Estimação de Movimento de Blocos de Tamanhos Variáveis do Padrão H.264/AVC
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A Novel Macroblock-level Filtering Upsampling Architecture for H.264/AVC Scalable Extension
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A Media Processing Implementation using Libvlc for the Ginga Middleware
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A Low Cost Real Time Motion Estimation/Compensation Architecture for the H.264/AVC Video Coding Standard
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A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement
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A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Interpolation Unit
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A Dedicated Hardware Solution for the H.264/AVC Half-Pixel Interpolation Unit
Livros publicados ou organizados (1)
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XVI Workshop Iberchip
2009 (25 publicações)
Artigos em periódicos (1)
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A Comparative Analysis of Media Processing Component Implementations for the Brazilian Digital TV Middleware
Trabalhos em eventos (21)
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Transforms and Quantization Design Targeting the H.264/AVC Intra Prediction Constraints
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System C Modeling of an H.264/AVC Intra Frame Video Encoder
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Modelos Arquiteturais de Alto Desempenho para as Transformadas 4×4 Diretas e Inversas do Padrão H.264/AVC
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Low Latency and High Throughput Dedicated Loop of Transforms and Quantization Focusing in the H.264/AVC Intra Prediction
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Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder
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Investigação Algorítmica sobre a Estimação de Movimento na Compressão de Vídeo Digital: Uma Análise Quantitativa
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High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard
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High Performance and Low Cost Architecture for H.264/AVC CAVLD Targeting HDTV
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Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding
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H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding
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Filtro Redutor de Efeito de Bloco Entre Camadas do Padrão H.264/AVC Escalável
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Efficient hardware design for the upsampling in the H.264/SVC scalable video coding extension
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Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering order
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Dedicated Architecture for the T/Q/IQ/IT Loop Focusing the H.264/AVC Intra Prediction
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Arquitetura de Alto Desempenho para o Algoritmo de Estimação de Movimento SDS-DIC com Múltiplos Quadros de Referência
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Arquitetura de Alto Desempenho e Baixo Custo para o Módulo de Quantização Direta do Padrão H.264/AVC de Compressão de Vídeo Digital
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Arquitetura Dedicada para o Loop de Transformadas e Quantização para a Predição Intra-Quadros do Padrão H.264/AVC
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A multitransform architecture for the H.264/AVC standard and its design space exploration
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A fast FPGA implementation of the inter-layer deblocking filter for H.264/SVC
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A Real Time H.264/AVC Main Profile Intra Frame Prediction Hardware Architecture for High Definition Video Coding
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A Real Time H.264/AVC Intra Frame Prediction Hardware Architecture for HDTV 1080P Videos
Livros publicados ou organizados (1)
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XXIV South Symposium on Microelectronics
Capítulos de livros (2)
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Investigação e Desenvolvimento de Hardware para as Transformadas do Padrão H.264/AVC de Compressão de Vídeo
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Investigação e Desenvolvimento de Algoritmos e Arquiteturas para a Estimação de Movimento em Vídeos Digitais
2008 (19 publicações)
Trabalhos em eventos (19)
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Transient Fault-Tolerant Fast Adders Implemented in FPGAS
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SystemC Modeling of an H.264/AVC Intra Frame Encoder Architecture
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Set-Tolerant Fast Adders Implemented in FPGAs
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Sensitivity Analysis to SETs Considering Timing and Logic Masking
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Implementation and Analysis of Architectures for the 4×4 2-D Forward Hadamard Transform of H.264/AVC.
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High Throughput Architecture for H.264/AVC Motion Compensation Sample Interpolator for HDTV
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HP422-MoCHA: A H.264/AVC High Profile Motion Compensation Architecture for HDTV
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Exploração da Multiprogramação Leve no Processo de Estimação de Movimento utilizando OpenMP
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Evaluating Fault-Tolerant Fast Adders Implemented in FPGAs
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Estimação de Movimento com Multiprogramação Leve
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Desenvolvimento de uma Arquitetura Paralela para a Hadamard 2-D 2×2 do Padrão H.264/AVC
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Arquitetura de Somador de Alto Desempenho Baseada no Recálculo Parcial com Carry Invertido.
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Arquitetura Dedicada à Decodificação dos Níveis do CAVLC Definido no Padrão H.264/AVC de Compressão de Vídeo
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Architectural Templates for the 4×4 Transforms Of the H.264/AVC Standard Targeting the Intra Prediction Coder
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Architectural Templates for the 4X4 Transforms of the H.264/AVC Standard targeting the Intra Prediction Coder
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Architectural Design for the New QSDS with Dynamic Iteration Control Motion Estimation Algorithm Targeting HDTV
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Architectural Design for Forward and Inverse Transforms of H.264/AVC Standard Focusing in the Intra Frame Coder
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Aplicação de Técnicas de Processamento Paralelo no Algoritmo Full Search de Estimação de Movimento
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A High Throughput and Low Cost Diamond Search Architecture for HDTV Motion Estimation
2007 (22 publicações)
Artigos em periódicos (4)
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Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
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Forward and Inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard
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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV
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Avaliação Algorítmica para a Estimação de Movimento na Compressão de Vídeos Digitais
Trabalhos em eventos (18)
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Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAS
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Reducing TMR Resource Overhead in Hardened Carry-Select Adders
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RIC Fast Adder and Its Set-Tolerant Implementation in FPGAS
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Preditor de Vetores de Movimento para o Padrão H.264/AVC Perfil Main
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Motion Compensation Hardware Accelerator Architecture for H.264/AVC
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MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV
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Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
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Investigation of Motion Estimation Algorithms Targeting High Resolution Digital Video Compression
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High Throughput Hardware Architecture for Motion Estimation with 4:1 Pel Subsampling Targeting Digital Television Applications
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High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard
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H.264/AVC HDTV Motion Compensation Soft IP
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FPGA Prototyping Strategy for a H.264/AVC Video Decoder
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FPGA Based Design of CAVLC and Exp-Golomb Coders for H.264/AVC Baseline Entropy Coding
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Desenvolvimento de Hardware para a Compensação de Movimento do Padrão H.264/AVC com Foco na Compressão de Vídeo do Sistema Brasileiro de Televisão Digital.
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Desenvolvimento Arquitetural para a Compensação de Movimento do Padrão H.264/AVC
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Arquitetura Completamente Paralela para o Bloco das Transformadas Diretas do Padrão H.264/AVC de Compressão de Vídeo
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A Pipelined 8×8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder
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A Motion Compensation Architecture Design and Prototyping Targeting SDTV Frames for H.264/AVC Standard
2006 (24 publicações)
Artigos em periódicos (2)
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Projeto de Hardware para a Compensação de Movimento do Padrão H.264/AVC de Compressão de Vídeo
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Codificador de Entropia Segundo o Perfil Baseline do padrão H.264/AVC de Compressão de Vídeo
Trabalhos em eventos (22)
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Validação de uma Arquitetura para Compensação de Movimento Segundo o Padrão H.264/AVC
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Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times
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Quantização Direta e Inversa de Alta Performance para a Compressão de Vídeo H.264/AVC Direcionada para HDTV
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Projeto de Arquiteturas Síncronas e de Alto Desempenho para os Blocos das Transformadas Diretas e Inversas da Compressão H.264/AVC
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Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV
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Investigação de Algorítmos e Proposta Arquitetural para a Estimação de Movimento Direcionada à Vídeos de Alta Resolução
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Investigação de Algoritmos e Desenvolvimento Arquitetural para a Estimação de Movimento em Compressão de Vídeo Digital
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High Throughput Multitransform and Multiparallelism IP for the H.264/AVC Video Compression Standard
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High Throughput FPGA Based Architecture for H.264/AVC Inverse Transforms and Quantization
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High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs
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High Throughput Architecture for H.264/AVC Forward Transforms Block
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Forward and Inverse 2-D DCT Architectures for H.264/AVC Video Compression Directed to HDTV
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FPGA Design of a H.264/AVC Main Profile Decoder for HDTV
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FPGA Based Architectures for H.264/AVC Video Compression Standard
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Exploração no Espaço de Projeto da Hadamard 4×4 Direta do Padrão de Compressão de Vídeo H.264/AVC
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Entropy Coder Architectures for H.264/AVC Baseline Profile
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Desenvolvimento de Hardware para a Compensação de Movimento do Padrão H.264/AVC com Foco na Compressão de Vídeo do Sistema Brasileiro de Televisão Digital
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Dedicated Hardware Architectures for H.264/AVC Exp-Golomb Coding and Decoding
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Avaliação dos Impactos do Uso de Somadores como Macro Functions em um Projeto de Compressor JPEG
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Arquitetura de Hardware Dedicada para a Decodificação Exp-Golomb do Padrão H.264 de Compressão de Vídeo
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Arquitetura Multi-Transformada de Alto Desempenho com Paralelismo Programável e Direcionada para o Padrão de Compressão de Vídeo H.264/AVC
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Análise Automática da Propagação de Single-Event Transients em Circuitos Combinacionais Implementados em FPGAs
2005 (15 publicações)
Artigos em periódicos (2)
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Comparison between OCP, PVCI and BVCI Hardware Reuse Interfaces Designed in VHDL and Mapped to FPGAs
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Arquiteturas de Cálculo da FDCT 2-D e da IDCT 2-D para Codecs HDTV no Padrão H.264/AVC
Trabalhos em eventos (13)
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Soft and Hard IP Design of a Multiplierless and Fully Pipelined 2-D DCT
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Projeto, Síntese e Simulação das Interfaces de Reuso de Hardware do Padrão OCP (Open Core Protocol)
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Motion Compensation Sample Processing for HDTV H.264/AVC Decoder
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Increasing the Image Quality in a JPEG Compressor through Arithmetic Error Minimization
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Impactos do uso de Diferentes Arquiteturas de Somadores em FPGAS Altera
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Hierarchical Timing Analysis Using Selective Critical Path Sensitization
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Hardware para o Compensador de Movimento do Padrão H.264 de Compressão de Vídeo
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Exploração do Espaço de Projeto em Arquiteturas para Cálculo da Raiz Quadrada Inteira
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Design and Comparison between PVCI, BVCI and OCP Hardware Reuse Interfaces Mapped to FPGA
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Design Space Exploration on the H.264 4×4 Hadamard Transform
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Desenvolvimento e Validação das Interfaces BVCI para o Reuso de Blocos de Hardware
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Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units
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A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor
2004 (8 publicações)
Artigos em periódicos (2)
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Parallel color space converters for JPEG image compression
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DomoWork: Ambiente para Projeto de Sistemas de Automação Predial\Residencial Orientado a Objetos
Trabalhos em eventos (6)
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Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation
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Experimentos com o Padrão de Reuso de Hardware OCP (Open Core Protocol)
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Experimentos com a Interface de Reuso PVCI em uma DCT 2-D Direcionada para a Compressão JPEG
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Experimentos com a Interface BVCI e com Projetos de Sistemas em Chip Baseados no Reuso de Hardware
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Experimentos com Somadores Rápidos para Uso na DCT 2-D
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Descrição e Validação das Interfaces de Reuso do Padrão OCP (Open Core Protocol) Utilizando VHDL
2003 (6 publicações)
Artigos em periódicos (1)
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Exploração do Espaço de Projeto da DCT 2-D de um Compressor de Imagens JPEG
Trabalhos em eventos (4)
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Experimentos com a Interface PVCI para Reuso de Blocos de Hardware
-
Error Minimization of 2-D DCT and Quantization Operations for a Gray Scale Images JPEG Compressor
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Design of Adder Architectures for JPEG Compression
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Conversor de Espaço de Cores Paralelo para a Compressão de Imagens JPEG
Livros publicados ou organizados (1)
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XVIII South Simposium on Microelectronics
2002 (2 publicações)
Trabalhos em eventos (2)
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Projeto de Arquitetura de Codificador de Entropia para Compressão JPEG de Imagens em Tons de Cinza
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Pipelined Entropy Coders for JPEG Compression
2001 (6 publicações)
Trabalhos em eventos (6)
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Projeto de uma Arquitetura de DCT 1D para a Compressão de Imagens JPEG
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Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
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Integrated Digital Architecture for JPEG Image Compression
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Caipirinha: A Free Graphical Viewer for Berkeley Spice
-
Arquitetura Integrada para Conversor de Espaço de Cores e Downsampler para a Compressão de Imagens JPEG
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A Dedicated 20 x 3 bit Multiplier Using the Recoding Principle for Echo Cancellation
2000 (6 publicações)
Trabalhos em eventos (6)
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Using Reconfigurability Features to Break Down Test Costs: a Case Study
-
SisECO: Design of an Echo-Canceling IC for Base Band Modems
-
Projeto de um Circuito Cancelador de Eco – SisECO
-
Modeling and Simulation of a Heterogeneous Embedded System
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Implementação de Filtros Adaptativos para Cancelamento de Eco
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Estudo de Cores a partir da Arquitetura Parte Operativa 2901