{"id":142,"date":"2022-10-03T17:03:01","date_gmt":"2022-10-03T20:03:01","guid":{"rendered":"https:\/\/wp.ufpel.edu.br\/dpvsa2022\/?page_id=142"},"modified":"2023-05-25T11:26:10","modified_gmt":"2023-05-25T14:26:10","slug":"palestrante-jose-luis-guntzel","status":"publish","type":"page","link":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/palestrante-jose-luis-guntzel\/","title":{"rendered":"Palestrante &#8211; Jos\u00e9 Lu\u00eds Guntzel"},"content":{"rendered":"<p style=\"text-align: center;\"><strong><span style=\"font-size: 24pt;\">Jos\u00e9 Luis G\u00fcntzel<\/span><br \/>\n<\/strong><strong><span data-sheets-value=\"{&quot;1&quot;:2,&quot;2&quot;:&quot;Institute of Informatics, Federal University of Rio Grande do Sul (UFRGS)&quot;}\" data-sheets-userformat=\"{&quot;2&quot;:513,&quot;3&quot;:{&quot;1&quot;:0},&quot;12&quot;:0}\">UFSC<\/span><br \/>\n<\/strong><\/p>\n<p style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-502\" src=\"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/files\/2023\/04\/avatar_jose-luis-guntzel.png\" alt=\"\" width=\"200\" height=\"246\" \/><\/p>\n<h3 style=\"text-align: center;\"><span style=\"font-size: 18pt;\"><em><span data-sheets-value=\"{&quot;1&quot;:2,&quot;2&quot;:&quot;Sustainable Video Streaming Systems&quot;}\" data-sheets-userformat=\"{&quot;2&quot;:577,&quot;3&quot;:{&quot;1&quot;:0},&quot;9&quot;:0,&quot;12&quot;:0}\">\u00a0Introduction to Chip Design Automation (EDA)<\/span><\/em><\/span><\/h3>\n<p style=\"text-align: center;\">Basic<\/p>\n<p style=\"text-align: center;\">Data: 30\/05 &#8211; 08:30<\/p>\n<p style=\"text-align: center;\">Chair: Mateus Grellert<\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-size: 14pt;\"><strong>Abstract<\/strong><\/span><\/p>\n<p style=\"padding-left: 40px; text-align: justify;\">TBD<\/p>\n<p><span style=\"font-size: 14pt;\"><strong>Biography<\/strong><\/span><\/p>\n<p style=\"text-align: justify; padding-left: 40px;\">Professor Titular do Departamento de Inform\u00e1tica e Estat\u00edstica (INE), no Centro Tecnol\u00f3gico (CTC) da Universidade Federal de Santa Catarina (UFSC). \u00c9 supervisor do N\u00facleo Interdepartamental de Microeletr\u00f4nica (NIME) da UFSC, col\u00edder do Grupo de Pesquisa em Automa\u00e7\u00e3o do Projeto de Sistemas Computacionais Embarcados e membro do Laborat\u00f3rio de Computa\u00e7\u00e3o Embarcada (ECL) da UFSC. Possui gradua\u00e7\u00e3o em Engenharia El\u00e9trica (1990), mestrado (1993) e doutorado (2000) em Ci\u00eancia da Computa\u00e7\u00e3o pela Universidade Federal do Rio Grande do Sul (UFRGS). Em 1996 realizou est\u00e1gio (doutorado-sandu\u00edche) no Laboratoire dInformatique, de Robotique et de Micro-\u00e9lectronique de Montpellier (LIRMM), da Universit\u00e9 Montpellier 2, Montpellier, Fran\u00e7a. Entre 2017 e 2019 foi coordenador do Programa de P\u00f3s-Gradua\u00e7\u00e3o em Ci\u00eancia da Computa\u00e7\u00e3o (PPGCC) da UFSC. Entre 2002 e 2007, foi professor adjunto no Departamento de Inform\u00e1tica da Universidade Federal de Pelotas (UFPel). \u00c9 membro da Association for Computing Machinery (ACM) e do Special Interest Group on Design Automation (SIGDA). \u00c9 membro s\u00eanior do IEEE. \u00c9 membro da IEEE Circuits and Systems Society, da IEEE Computer Society (CS), da IEEE Signal Processing Society (SPS), do IEEE Council for Electronic Design Automation (CEDA), da Sociedade Brasileira de Computa\u00e7\u00e3o (SBC) e da Sociedade Brasileira de Microeletr\u00f4nica (SBMicro), da qual foi membro da diretoria na gest\u00e3o 2006-2008. Atualmente, \u00e9 o coordenador do IEEE Brazil CEDA Chapter, coordenador do Comit\u00ea Executivo (Steering Committee) do SBCCI (Symposium on Integrated Circuits and Systems Design) e membro do Comit\u00ea Gestor da Comiss\u00e3o Especial de Concep\u00e7\u00e3o de Circuitos e Sistemas Integrados da SBC. Tem experi\u00eancia nas \u00e1reas de Engenharia El\u00e9trica e Ci\u00eancia da Computa\u00e7\u00e3o, com \u00eanfase em Microeletr\u00f4nica, atuando principalmente nos seguintes temas: Electronic Design Automation (placement &amp; routing, gate sizing, clock tree synthesis, timing analysis etc), arquiteturas VLSI para compress\u00e3o de v\u00eddeos de alta resolu\u00e7\u00e3o e projeto de sistemas em chip (SoCs) de alta efici\u00eancia energ\u00e9tica.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Jos\u00e9 Luis G\u00fcntzel UFSC \u00a0Introduction to Chip Design Automation (EDA) Basic Data: 30\/05 &#8211; 08:30 Chair: Mateus Grellert &nbsp; Abstract TBD Biography Professor Titular do Departamento de Inform\u00e1tica e Estat\u00edstica (INE), no Centro Tecnol\u00f3gico&#46;&#46;&#46;<\/p>\n","protected":false},"author":746,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-142","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/pages\/142","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/users\/746"}],"replies":[{"embeddable":true,"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/comments?post=142"}],"version-history":[{"count":9,"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/pages\/142\/revisions"}],"predecessor-version":[{"id":769,"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/pages\/142\/revisions\/769"}],"wp:attachment":[{"href":"https:\/\/wp.ufpel.edu.br\/emicrosim2023\/wp-json\/wp\/v2\/media?parent=142"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}