Fernanda Kastensmidt
UFRGS (Brazil)
Exploring Fault Tolerant Topologies of Neural Networks in SRAM-based All Programmable System on Chip (APSoC) in Harsh Environments
Language: Portuguese
Date: TBD
Abstract
This talk presents recent advances in the design of fault-tolerant AI accelerators implemented on SRAM-based FPGAs for Earth observation applications in space environments. The increasing use of on-board processing in satellites enables real-time analysis of images captured from orbit, reducing communication bandwidth with ground stations and enabling faster decision making. Convolutional Neural Networks (CNNs) can be embedded into FPGA-based systems combining processors and hardware accelerators to perform tasks such as classification and object detection in satellite imagery. However, electronics deployed in space are exposed to radiation effects such as Total Ionizing Dose (TID) and Single Event Effects (SEEs), which may cause bit-flips, transient faults, or long-term degradation of electronic devices. These effects are particularly critical in SRAM-based FPGAs, where configuration memory upsets can alter the functionality of the logic that has been customised into the FPGA. The tutorial discusses the architecture of system-on-chip platforms integrating a RISC-V processor and AI accelerators implemented on FPGAs, exploring different accelerator designs such as FINN, ZynqNet, and systolic arrays. The design challenges associated with implementing CNNs in FPGA devices—such as limited computational resources, memory bandwidth, power constraints, and real-time processing requirements are analyzed. To ensure reliable operation in radiation-prone environments, the tutorial introduces fault-tolerant design techniques, including Triple Modular Redundancy (TMR), configuration scrubbing, and error detection and correction mechanisms. Methods for evaluating reliability using fault injection campaigns targeting FPGA configuration memory are also presented. Through real case studies, including satellite missions and Earth-observation datasets such as SAT-6, the tutorial demonstrates how hardware/software co-design can enable robust AI processing in space applications.
Biography
Fernanda Kastensmidt holds a degree in Electrical Engineering from the Federal University of Rio Grande do Sul (1997), a Master’s degree in computer science from the Federal University of Rio Grande do Sul (1999) and a PhD in Computer Science from the Federal University of Rio Grande do Sul (2003). Fernanda is a Full Professor at the Federal University of Rio Grande do Sul and was Coordinator of the Postgraduate Program in Microelectronics (PGMICRO) for 4 years and was Head of the Department of Applied Informatics for 2 years. She is currently the Administrative Director of the Brazilian Society of Microelectronics (SBMICRO). She has experience in the area of Microelectronics and Computer Engineering, with an emphasis on Hardware, working mainly on the following topics: radiation fault protection techniques, fault-tolerant system design, programmable architecture, FPGA, RISC-V processors, AI accelerators, qualification of systems and integrated circuits under faults and fault modeling. She is the author of the book Fault Tolerance Techniques for SRAM-based FPGAs published in 2006 by Springer and co-author of 3 other scientific books. She participated in the project of the payload of the NanoSat-BR1 satellite that was launched in June 2014 and NanoSat-BR2 where part of the payload is responsible for analyzing the effects of SAA on Integrated Circuits manufactured in nanometric technology launched in 2021.